The present invention relates to a memory system, and more particularly to a low-cost and high speed memory controller, a memory module and a memory system.
In memory controlling system, a DDR3 SDRAM (Double-Data-Rate Three Synchronous Dynamic Random Access Memory) interface with single-end signals is very sensitive to external environments, such as chip package type and system board design. In order to guarantee the system performance, IP (Intellectual Property) providers of the memory controller often define the package and PCB (Printed Circuit Board) design constraints to reduce product risks. These design constraints may increase the package size and DDR3 PCB area to cost up the whole system cost. More specifically, for the Chip Select (CSN) signal of the conventional DDR3 SDRAM memory interface, a regulator, i.e. the so called Vtt regulator, is often used to provide a predetermined voltage level at the termination of the conducting path of the CSN signal to reduce the reflection of the CSN signal so that to guarantee the signal integrity in DDR3 applications. However, this Vtt regulator increases the BOM (Bill of Material) cost of the memory controller. Therefore, to introduce a novel memory system to reduce the BOM cost and to relax the external environment requirement of the memory controller is an urgent problem in the field of memory controlling system.